1. Field of the Invention
The present invention relates to an elastic buffer circuit for delaying communication data input thereto and then outputting this data, and particularly to an elastic buffer circuit for operating in synchronism with an input clock pulse and an output clock pulse having almost the same frequencies, each including a frequency variation therein.
2. Description of the Prior Art
In digital communication devices, for example, a configuration as shown in FIG. 1 is known as an elastic buffer circuit to be inserted in an input and output path to delay communication data.
In this diagram, a delay buffer circuit as the elastic buffer has a memory portion 1 for storing input data and then outputting the data, a writing pointer 3 for controlling the writing of the data input to the memory portion 1, a reading pointer 5 for controlling the reading of the data output from the memory portion 1 and an error detector 7 for detecting an error generated in the writing and reading operation.
In the memory portion 1, data to be input thereto is successively contained in memory elements selected from n memory elements (a position #0 to a position #n-1) by a decoder 9. The data contained in the memory elements is selected by a selector 13, and then output as output data.
Namely, binary numbers of 0 to n-1 designating memory elements (where the binary number is a number of m figures (n&lt;=2.sup.M), hereinafter called a "writing position code") is output from the writing pointer 3 in synchronism with an input clock. Then, each writing position code is decoded by the decoder 9. Thereafter the input data is successively stored in the memory elements based on each decoded result.
Binary numbers of 0 to n-1 designating memory elements (the binary number will be called a "reading position code" hereinafter) is output from the pointer 5. Then, data stored in the respective memory elements is selected and output based on the respective reading position codes by the selector 13.
In the operation for delayed input data, when the operation is starting, a code having an interval of n/2 with respect to an initial code of the reading pointer 5 is set as a writing initial code designated by the writing pointer 3, where n is the number of memory elements. For example, assuming that the number of memory elements is 12 (n=12), when the input data is successively stored in the memory elements from the memory element designated by a position #0 based on the writing position codes, the output data is successively read out of the memory elements from the element designated by a position #6 based on the reading position codes. In such a manner, an attempt is made to cause a frequency variation of the input clock pulse with respect to the output clock pulse to be absorbed by setting a sufficiently large interval between the reading position code and the writing position code.
However, in the elastic buffer circuit comprising the above-mentioned configuration, the frequency variations of the input clock and output clock pulses cause errors such as underflow, in which the number of data units to be stored in the memory elements becomes less than 0, and overflow, in which the number of data units becomes greater than n.
For example, in the case of a frequency variation in which the frequency of the input clock pulse is a little lower than that of the output clock pulse, the number of data units to be stored is gradually reduced and finally becomes less than 0. At that time, when the writing pointer 3 and the reading pointer 5 designate the same memory element, as shown in FIG. 3, since the frequency of the output clock pulse is high, an underflow error in which data is read before completion of the writing of the data into the memory elements is caused. Otherwise, the reading is carried out immediately after the completion of the writing as shown in FIG. 4, so that it becomes difficult to stably output the data.
Also, in the case of a frequency variation in which the frequency of the input clock pulse is a little higher than that of the output clock pulse, the number of data units to be stored is gradually increased and finally becomes greater than n. At that time, when the writing pointer 3 and the reading pointer 5 designate the same memory element, as shown in FIG. 5, an overflow error in which the next data is written in the same memory element before completion of the reading of the data occurs.
Such errors are detected by the error detector 7. When the error detector 7 detects an error, it outputs an error detection signal on condition that either the equation EQU K=L(K-L=0)
when an overflow error is caused, or EQU K=L-1(K-L=1)
when an underflow error is caused is satisfied.
Where K is the position of the memory element designated by the writing pointer 3, and L is the position of the memory element designated by the reading pointer 5.
When a frequency variation occurs in the input clock pulse or in the output clock pulse, an error operation such as those mentioned above is likely to be caused. Accordingly, when the error occurs, the writing and the reading should be temporarily stopped, and the writing position code and the reading position code reinitialized and returned to normal operation.
As stated above, the error operation is detected by the difference between the values of the writing position code and the reading position code respectively cycling from 0 to n-1 and judging whether the difference is 0 or 1. Thus, a complex configuration is required for the circuits for calculating the difference in the codes respectively cycling from 0 to n-1.
Moreover, the writing position code and the reading position code are respectively composed of a plurality of bits so that the difference between the codes is also composed of a plurality of bits. Accordingly, the values of the bits for designating the difference are not stably fixed until the input and the output operations of the data are completed and the respective position codes are fixed. The error detection signal is output at that time. However, since the input and output operations are carried out at different times respectively based on the input clock pulse and the output clock pulse, including frequency variations, it is extremely difficult to obtain timings for stably fixing the difference of the respective position codes. Therefore, it is difficult to distinctly judge whether the difference of the respective position codes is 0 or 1, thus an occurrence of the error operation can not be detected correctly in the prior art.
In the initialization of the pointing means, the writing position code and the reading position code, as described above, the writing pointer having the writing position code and the reading pointer having the reading position code should be suitably set out not only at the start of the operation, but also after detection of the error operation and when normalizing the delay time. However, since the number of data units in memory elements is not fixed because of frequency variation, it is extremely difficult to initialize the distance of both position codes without losing valid data. For example, when the number of the valid data units is more than n/2 and the distance of both the positions is set at n/2, a portion of the valid data is inevitably lost.
Moreover, when the initialization is carried out during the operation of the elastic buffer circuit, in order to set a code obtained by addition of n/2 to a reading code of the reading pointer 5 as an initial writing value of the writing pointer 3, an additional circuit for calculating the above code is required, so that the size of the elastic buffer circuit must be increased.
Incidentally, the additional operation for calculating the code must change values of a plurality of bits in the code, and each value of the bits can not be fixed at the same time. Furthermore, since the calculation to decide the timing of the initialization can not be carried out in synchronism with the input clock pulse, the initial code can not be set as a correct writing initial code. In this case, normal operation cannot be obtained even when the pointing means are initialized.